Posted by Applying Development Cycle Electronics Hardware Sub-Product Cost Models to Project Execution
Models and Methods Track
MM05_Presentation_DevelopmentCycleElectronicsHardwareSubProductCostModels_Bloom
Abstract:
Over the last decade, many advances have been accomplished by notable organizations in applying parametric model techniques to establish cost estimates for deliverable electronics systems and electronics products. At the Electronics Center of Raytheon Space and Airborne Systems, we utilize commercial software applications to perform these kinds of tasks.
However, the Electronics Center also collects and analyzes development cycle cost and size relationship data at the electronics sub-product level. Electronics sub-products would be considered items like Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs) and Analog and Digital Modules. While the primary purpose for developing parametric models for the development cycle at the sub-product level is to estimate the cost of new business activities, it will be shown that the model is equally essential in developing leading indicators for in-process development cycle execution.
This paper discusses the concept of “effective size” and “effective productivity” and how, when matched to Earned Value (EVMS) concepts, these parameters become leading indicators for cost over-run at the sub-product level. Fundamental to this discussion is that if a task has a cost over-run, then either it grew in “effective size” from that estimated or the “effective productivity” is lower than expected.
Among the other topics covered are choosing the best form for the parametric cost model for working in the “effective size” and “effective productivity” state space and methods to perform coordinate transformation when the existing cost model does not match the “effective size”/”effective productivity” paradigm.
Author:
David Bloom
Raytheon Space and Airborne Systems
After graduating from the University of California at Davis in 1983, Mr. Bloom has worked for the Naval Weapons Center, Lockheed Martin, Lawrence Livermore National Labs and since 2008, for Raytheon Space and Airborne Systems (SAS) where he is a Sr. Engineering Manager.
Mr. Bloom is currently the Cost Estimation Subject Matter Expert (SME) for the Electronics Center of SAS. He has developed parametric models for all Electronics Center products and helped transform the culture of the organization in the use of parametric bidding methodologies. As part of his SME responsibilities, David is responsible for integrating SEER -H cost estimation into the hardware development organization.
Mr. Bloom’s focus for the Electronics Center has been on developing parametric cost models for the design and development cycle activity of electronics sub-products. The sub-products include components (e.g. Field Programmable Gate Arrays, FPGAs), modules (e.g. digital modules, analog modules and RF modules) and units (e.g. digital units, analog units, RF units, special test equipment and antennas).
Under David’s leadership, the Raytheon SAS Electronics Center is now in its 4th generation of parametric cost models for electronics hardware and is soon moving to web hosted cost estimation activities that include Monte Carlo simulation and Web 2.0 collaboration capabilities.
Mr. Bloom has 2 patents and a software copyright along with a number of publications.